As is well known by those skilled in the art, a continuing goal in manufacturing and production of memory devices is increased storage in the minimum area or least amount of silicon. Flash memory is programmable, erasable and non-volatile. The basic flash memory cell is a planar NMOS transistor that has been modified with a “floating” gate. A conventional flash memory cell is programmed by applying a high voltage to the control gate or the word line and a high voltage to the drain by way of the bit line. These voltages excite the electrons such that they push through the thin oxide layer and are trapped on the floating gate. Consequently, the gate carries a negative charge. If the negative charge on the floating gate is above a selected threshold level, the bit stored in the cell is defined as a “zero.”
A flash memory cell programmed with a “zero” may be erased by applying a high voltage to the gate and leaving the drain or bit line open or floating. Thus, the excess electrons that were trapped on the floating gate now move to the gate so that the floating gate is again neutral, which is defined as a “one”. To “read” the cell, an operation voltage is applied to the gate. If the transistor is turned on, its drain output is a high current and is defined as a “one”. If the transistor is not on, its drain is a low current, which is defined as “zero.” Thus, the floating gate planar NMOS transistor provides a high-speed non-volatile memory cell.
As the demand increases for larger and larger non-volatile high-speed memories, the typical answer has been to aggressively decrease the geometry or size of a memory chip and simply pack more memory cells in the same area. However, demand and need is increasing faster than can be accommodated by scaling or decreased geometry. Consequently, there have now been developed dual-bit flash cells that can provide two data bits per cell and effectively double the amount of storage in an array. Flash memory cells that can store two bits do so by using four different precise voltages to represent the state of the two bits. For such flash memory cells, the manufacturing process has little margin for variance to form floating gates that can be charged to precise voltage settings. Furthermore, the circuitry for providing the necessary word line, bit line and gate voltages to achieve the necessary threshold electron charges and resulting voltages is also significantly more complicated.
Accordingly, it is desirable to provide a nonvolatile memory cell with an improved structure, such as a dual-bit NVM cell. In addition, it is desirable to provide improved methods for fabricating integrated circuits including nonvolatile memory structures. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.